ADP5022
Rev. C | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Rating
VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2,
VOUT3, EN1, EN2, EN3, MODE to GND
0.3 V to +6 V
Storage Temperature Range
65癈 to +150癈
Operating Junction Temperature Range
40癈 to +125癈
Soldering Conditions
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP5022 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature (TA) does
not guarantee that the junction temperature (TJ) is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature may exceed the maximum
limit as long as the junction temperature is within specification
limits. TJ of the device is dependent on TA, the power
dissipation (PD) of the device, and the junction-to-ambient
thermal resistance (?/DIV>
JA
) of the package. Maximum T
J
is
calculated from T
A
and P
D
using the following formula:
T
J
= T
A
+ (P
D
??/DIV>
JA
)
?/DIV>
JA
of the package is based on modeling and calculation using a
4-layer board. The junction-to-ambient thermal resistance is
highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of ?SPAN class="pst ADP5022ACBZ-6-R7_2465982_6">JA may vary, depending on PCB material, layout, and envi-
ronmental conditions. The specified values of ?SPAN class="pst ADP5022ACBZ-6-R7_2465982_6">JA are based on a
4-layer, 4 ?3 circuit board. Refer to JEDEC JESD 51-9 for
detailed information on the board construction. For additional
information, see the AN-617 Application Note, MicroCSP
TM
Wafer Level Chip Scale Package.
THERMAL RESISTANCE
?/DIV>
JA
is specified for the worst-case conditions, that is, a device
soldered on a circuit board.
Table 5. Thermal Resistance
Package Type
?/DIV>
JA
Unit
16-Ball, 0.5 mm Pitch WLCSP
65
癈/W
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